Module fpga_decode 

A decode on one ZCU104: what the board holds, how fast its programmable logic reads it, and what a token of each checkpoint we have costs there.

The ZCU104’s XCZU7EV keeps 4.98 MB in its block RAMs and UltraRAMs, and reaches the board’s 2 GB of DDR4 only through the processing system: the programmable logic reads it over 128-bit AXI HP ports, each moving 16 bytes a PL clock cycle, all behind one DDR4-2400 controller on a 64-bit bus. So the board’s decode rate is set by the PL clock and how many ports the fabric drives, an operating point rather than one number, and zcu104_points names the three that bound it: four ports at 100 MHz, which the FPT’19 study measured saturating on the ZCU102 (the same processing system, the same DDR4 rate and width); three ports at 300 MHz, its best measured read at 75% of the DDR’s peak; and the DDR’s peak itself.

zcu104_sizing prices every local checkpoint at each point with price: the floor no implementation on the board can beat, where the weights live, and the term that binds.

Structs

ModelSizing

One checkpoint on the board.

PlPoint

One way the programmable logic can run against the DDR: its clock, the HP ports it reads through, and what those ports read.

PointSummary

One operating point, as the sizing states it.

SizingRow

A checkpoint at one operating point.

Zcu104Sizing

Every local checkpoint, priced on the ZCU104 at each operating point.

Enums

Fit

Whether a checkpoint fits the board.

Constants

FPT19

HP_PORT_BYTES

Bytes one 128-bit AXI HP port carries in a PL clock cycle.

UG1267

WP486

ZCU104_CTX

The context the sizing’s KV caches have reached.

ZCU104_MODELS

The checkpoints the sizing prices: every local one, in benchmarks/silicon/decode/headers/.

Functions

ddr_capacity

The DDR4 behind the processing system, as the board guide states it.

ddr_peak

What the DDR4 itself moves at most: its transfer rate times its bus width.

zcu104

The ZCU104 at its four-port, 100 MHz point: the one the catalog prices.

zcu104_at

The ZCU104 at p. Its SRAM is the part’s block RAMs and UltraRAMs, read on every port at the PL clock; its DDR is the board’s, read at what the point’s ports read; its matrix rate is two int8 multiply-accumulates per DSP slice per PL cycle. Facts computed from the clock are as strong as the clock.

zcu104_points

The operating points that bound a ZCU104 decode, slowest first. The first is the catalog’s zcu104.

zcu104_sizing

The sizing, read from the header ledgers in decode_dir.