Module decode_chip 

The decode chip — what an SRAM-resident LOGOS system must achieve to decode one user faster than GPUs can.

super::decode prices a token on any machine. This module turns the question around: given a checkpoint, a GPU deployment’s FLOOR (its memory roofline with every overhead at zero — the most a GPU could ever do) and a speedup, it asks what a system of LOGOS chips must achieve, and answers in the units a chip is designed in.

★ AT BATCH ONE ON SRAM, BANDWIDTH IS NOT WHAT BINDS. Weights held in on-die SRAM across enough chips stream in microseconds; what remains is the CHAIN — a token walks every block’s dependent stages (norm, projection, mixer, projection, all-reduce, …), and each one costs its on-chip latency (the input vector out to every tile, the partial sums back) plus, where it reduces across chips, its collective’s hops. So the answer is a pair of latency budgets: the most one dependent stage may take on chip, and the most one chip-to-chip hop may take, for the system to beat the GPU floor by the speedup. demonstrated_stage_latency reads the same quantity back out of the vendors’ published per-user rates, so a budget can be set against what an SRAM machine has actually shown.

The chip is a design point (DecodeChipDesign): a die area, the share of it that is SRAM, the SRAM per tile and the on-chip network’s shape are CHOICES; the node’s SRAM density, read width and clock are FACTS (Node) with sources. Every number the design derives is therefore labeled modeled: a design is not a part.

Structs

DecodeChipDesign

A decode chip design point: the choices, over a node’s facts.

DecodeChipReport

The decode-chip report: what a LOGOS system must achieve, checkpoint by checkpoint.

Demonstrated

A vendor’s published per-user rate, and the per-stage latency it implies.

GpuFloor

A GPU deployment’s floor on one checkpoint.

ModelReport

Everything the report says about one checkpoint.

Node

A process node, as an SRAM decode chip sees it.

Requirement

What a LOGOS system must achieve to beat a GPU deployment’s floor by a speedup on one checkpoint.

RequirementRow

One requirement: a GPU baseline, the speedup over its floor, the design asked to reach it, and the answer.

Enums

OnChipNetwork

How a dependent stage’s vector reaches every tile and its partial sums come back.

Constants

REPORT_MODELS

The checkpoints the report prices, by header ledger name.

Functions

demonstrated_stage_latency

The per-stage latency a published per-user rate implies: everything a token took beyond its memory floor, spread over its dependent stages. A rate this machine reached is a latency it has shown.

fewest_chips

The fewest chips of chip that hold step.

report

The report over the header and published ledgers under decode_dir (benchmarks/silicon/decode).

requirement

What design must achieve to decode step at target_tok_s.

ucie_link

The die-to-die link a decode system’s chips connect with, at a hop latency the requirement solves for: modules UCIe standard-package modules striped together.