Module d5005 

The Intel PAC D5005: a Stratix 10 SX 2800 on four channels of DDR4, as a decode card.

The card’s facts are its data sheet’s, its shell’s and its device’s resource table’s. What a design adds to them is an EnginePlan: how many DSP blocks multiply 4-bit weight codes, two products to each of a block’s two 18×19 multipliers; how many soft multiply-adds the logic carries beside them; how many block-scale lanes turn the array’s integer sums into f32, and the DSP blocks and logic they take; how many DSP blocks run in f32 for the vector units; how much of each DDR4 beat carries data; how many lines of a recurrent state the stream engines read before writing them back; and the clock the array closes at. Until the engine is fitted the clock, the soft multiply-adds and the lanes’ logic are modeled, and every price that rests on them says so. Until the card’s stream receipt is taken, the share of the DDR4 peak each way a pass moves its bytes sustains is the DDR4 ledger’s (DDR_STREAMS): the shell’s own controller timing, issued by the JESD79-4 controller model.

roofline prices Qwen3.8-27B on the card at every knob point of the decode engine, one trick at a time, from the checkpoints’ own headers: what each trick buys, which term binds, and how many sequences fit.

Re-exports

pub use super::part::S10_OVERVIEW;

pub use super::part::S10_PRODUCT_TABLE;

Structs

BeatStreams

One beat’s streams in the DDR4 ledger (benchmarks/silicon/d5005/ddr4_efficiency.json, written by super::decode_engine::ddr::ddr_ledger from the shell’s EMIF timing through the JESD79-4 controller model), in the ledger’s order: a long read of weights; a Gated-DeltaNet memory read and written back STATE_CHUNKS lines at a time; a cache read with its new position appended after it, at each of CACHE_POSITIONS.

EnginePlan

How the decode engine spends the device: the multiplier budget, the block-scale lanes, the memory beat and the clock it closes at.

FullBeat

Roofline

RooflineRow

One knob point of the engine and its price at the batch that emits the most tokens per second.

StreamClocks

The clocks a channel carried data in of the clocks one stream took, as the DDR4 ledger counts them.

Enums

Beat

How much of each DDR4 beat carries data.

Constants

ACCEPTANCE_LEDGER

The ledger the measured MTP acceptance is read from.

ACCEPTANCE_POINTER

The JSON pointer of the one-draft acceptance measured on Qwen3.8-27B.

ALMS

Adaptive logic modules.

ARRAY_MACS_PER_DSP

Products of a 4-bit weight code and an 8-bit activation code one DSP block retires per cycle: each of its two 18×19 multipliers takes an activation code on one port and two rows’ weight codes on the other, so two rows’ products leave every multiplier in disjoint lanes (decode_engine::rtl::array).

CONTEXT_SWEEP

Context limits the sweep allows its sequences, each halfway through its limit: up to the checkpoint’s own.

D5005_DATA_SHEET

The card’s data sheet.

D5005_FIM_EMIF

The card’s shell: its four memory controllers built without ECC, each exposing all 72 bits of a beat.

D5005_OFS_GUIDE

The Open FPGA Stack guide for the card: its shell’s memory and host interfaces.

D5005_SOURCES

DDR_BYTES_PER_TRANSFER

DDR_CHANNELS

DDR4 channels, the transfers per second of each and the bytes per transfer (64 data bits; ECC beside them).

DDR_CHANNEL_BYTES

Bytes each channel’s DIMM holds: 1 Gi words of 64 data bits.

DDR_STREAMS

The DDR4 ledger’s streams at both beats.

DDR_TRANSFERS_PER_S

DRAFT_HEAD_ROWS

Vocabulary rows the drafting head reads when it keeps only the most frequent tokens.

DSP_BLOCKS

DSP blocks on the device: half its 18×19 multipliers, two to a block.

KV_PAGE

Positions per KV page.

LANE_MIX

Array cycles per lane cycle the standard plan’s lanes keep up with: Qwen3.8-27B Q4_K_M’s own mix, its K-quant matrices a lane cycle per 256 elements, its Q8_0 matrices one per 32 over two passes, its drafting layer’s Q4_0 one per 32, with room for the drafting layer.

M20K_BITS

M20K_BLOCKS

M20K blocks and the bits each holds.

PCIE3_SPEC

The host link’s signalling.

PCIE3_X16_BYTES_PER_S

Bytes per second one direction of the PCIe Gen3 x16 host link carries: 16 lanes of 8 GT/s, 128b/130b.

SCALE_LANE_DSPS

DSP blocks one block-scale lane takes: its block scale times the activation scale times the block’s integer sum and its second scale’s alike, two 27×27 products, and its f32 accumulate.

Functions

card

The card as a serving sees it, under plan.

chip

The card as a batch-one decode sees it: the M20K blocks and the DDR4 behind them.

host_link

The host memory the card reaches over PCIe Gen3 x16, both directions at once.

ladder

The engine’s knob points, one trick added at a time, then every trick at every weight format.

measured_acceptance

The one-draft acceptance, as measured.

mixed

A serving’s mix of chats, documents and long contexts: 70% of sequences at 512 of 2,048 positions, 25% at 4,096 of 8,192, 5% at 65,536 of 131,072.

roofline

Every knob point of ladder priced on the card under the standard plan, at its fastest batch.

streams

The shares of the card’s DDR4 the stream engines sustain under plan, from the ledger’s streams at its beat: the weights’ long read; the state rewritten at the plan’s chunk; the least of the caches’, which holds at every context the ledger prices.

weakest

The weakest provenance of every fact a roofline row rests on.