Module xpu_soc_rtl 

xpu_soc_rtl — Stage 6 of the self-synthesizing bytecode XPU: the SoC that receives a block’s BYTECODE OVER THE WIRE, parses it on-chip, and runs it on the reconfigurable execute engine — the north star made physical (in simulation). A block’s decoded op list is serialized to a byte stream (the wire format); the SoC clocks the bytes in one at a time into an on-chip buffer, assembles them into the engine’s config + inputs, and the engine computes the result — no host help beyond the bytes on the wire.

Wire format (big-endian), matching block_stream_bytes: for each of k cells, [ctrl:4][a_const:8] [b_const:8] (20 bytes), then [result_idx:2], then in[j]:8 for each of n_in inputs. The SoC counts bytes into a buffer, raises done when the whole frame has arrived, and drives result combinationally from the assembled config. This is nexys_soc.v’s load-then-run pattern, but the payload configures the spatial execute engine instead of the sequential soft-core.

Proven ≡ the VM under iverilog by xpu_soc_lock: for a corpus, streaming a program’s bytecode bytes makes the SoC compute exactly what the VM computes. (The engine compute mirrors block_engine_rtl — a candidate for a shared core once the SoC grows the sequencer + state-plane BRAM.)

Functions

block_stream_bytes

Serialize a block’s config + one input vector into the SoC’s big-endian wire byte stream.

emit_xpu_soc_testbench

A self-checking testbench: clock a program’s bytecode frame in byte-by-byte, wait for done, and compare result to the VM oracle. One frame carries the config + one input vector, so a frame is streamed per (program, input) case; rst clears the loader between frames.

emit_xpu_soc_verilog

Emit the XPU SoC: a byte-stream loader (byte_in/byte_valid) filling an on-chip frame buffer, on-chip assembly of the engine’s config + inputs, and the k-cell execute engine — done + result when the whole frame has arrived.