Struct WImage 

pub struct WImage {

    pub n_blocks: usize,
    pub n_params: usize,
    pub nreg: usize,
    pub blk_livein_ptr: Vec<u32>,
    pub blk_n_livein: Vec<u32>,
    pub blk_cell_ptr: Vec<u32>,
    pub blk_n_cells: Vec<u32>,
    pub blk_write_ptr: Vec<u32>,
    pub blk_n_writes: Vec<u32>,
    pub blk_term_kind: Vec<u32>,
    pub blk_t0: Vec<u32>,
    pub blk_t1: Vec<u32>,
    pub blk_top: Vec<u32>,
    pub blk_cdst: Vec<u32>,
    pub blk_cargc: Vec<u32>,
    pub blk_cargp: Vec<u32>,
    pub cell_kind: Vec<u32>,
    pub cell_code: Vec<u32>,
    pub cell_op0: Vec<u32>,
    pub cell_op1: Vec<u32>,
    pub cell_op2: Vec<u32>,
    pub cell_op3: Vec<u32>,
    pub wr_reg: Vec<u32>,
    pub wr_op: Vec<u32>,
    pub arg_op: Vec<u32>,
    pub liv_reg: Vec<u32>,
    pub konst: Vec<i64>,
}

The flat, loadable image of a whole program: parallel per-field arrays the generic engine reads directly. Block b’s fields are blk_*[b]; its cells are cell_*[blk_cell_ptr[b] .. + blk_n_cells[b]]; and so on.

Fields

n_blocks: usize

n_params: usize

nreg: usize

blk_livein_ptr: Vec<u32>

blk_n_livein: Vec<u32>

blk_cell_ptr: Vec<u32>

blk_n_cells: Vec<u32>

blk_write_ptr: Vec<u32>

blk_n_writes: Vec<u32>

blk_term_kind: Vec<u32>

blk_t0: Vec<u32>

blk_t1: Vec<u32>

blk_top: Vec<u32>

blk_cdst: Vec<u32>

blk_cargc: Vec<u32>

blk_cargp: Vec<u32>

cell_kind: Vec<u32>

cell_code: Vec<u32>

cell_op0: Vec<u32>

cell_op1: Vec<u32>

cell_op2: Vec<u32>

cell_op3: Vec<u32>

wr_reg: Vec<u32>

wr_op: Vec<u32>

arg_op: Vec<u32>

liv_reg: Vec<u32>

konst: Vec<i64>

Implementations

impl WImage

pub fn hex_files(&self) -> Vec<(String, String)>

The $readmemh payloads for every field memory, as (memory-name, hex-lines) pairs. An EMPTY memory still emits one 0 line so $readmemh has a file to read (the engine never indexes an empty pool).

impl WImage

pub fn wire_bytes(&self, params: &[i64]) -> Vec<u8>

The exact byte stream a host sends OVER THE WIRE to the wpe_soc engine: for each of the 24 config memories (the hex_files order) a 2-byte big-endian entry count then that many big-endian words (4 bytes for the 23 u32 memories, 8 for konst), then a 2-byte param count + that many 8-byte params, then the IMAGE_GO marker. The on-chip loader FSM reproduces the identical config in on-chip memory — so the chip SYNTHESIZES the program it is handed. Single source of truth for both the iverilog host and the FPGA host.

pub fn wire_bytes_preloaded(&self, params: &[i64], heap_init: &[i64]) -> Vec<u8>

As Self::wire_bytes but with an optional HEAP PRE-LOAD segment — the streamed-weights path. heap_init is loaded into heap[0..heap_init.len()] before the run (the DATA-segment model), so loaded() (heap pointer 0) reads it; the engine seeds its bump allocator past the pre-load and clears only the runtime region. The segment is BACKWARD-COMPATIBLE and marker-delimited: when heap_init is empty the stream is byte-identical to wire_bytes (…params + IMAGE_GO); when non-empty, an IMAGE_HEAP marker after the params introduces a u16 word-count then that many u64 words, then the IMAGE_GO byte. So a non-streamed program’s wire format is unchanged (the loader sees IMAGE_GO right after the params) and only streamed programs carry the extra segment.

Trait Implementations

impl Default for WImage

fn default() -> WImage

Returns the “default value” for a type.