Function emit_wprog_verilog 

pub fn emit_wprog_verilog(name: &str, cfg: &WProgConfig) -> String

Emit the WHOLE-PROGRAM ENGINE as synthesizable RTL: a register file + block-PC + a SEQUENTIAL per-cell datapath (one cell per clock into a cell-value array v, so the ordered HEAP STATE PLANE — HeapRead / HeapWrite / HeapAlloc against a heap BRAM — threads exactly as the model does) + a terminator FSM (Jump/Branch/Return/CALL) + a FRAME STACK that saves the caller’s register file on every Call and restores it on Return. So the WHOLE language family — branchy control flow, loops, recursion, division, and collections/strings/structs on the heap — runs on silicon, proven bit-identical to eval_wprog_config (≡ the VM) under iverilog. Cells: Arith / Select / Func (divider) / HeapRead / HeapWrite / HeapAlloc.