Function emit_wprog_engine_soc_verilog_synth 

pub fn emit_wprog_engine_soc_verilog_synth(name: &str) -> String

Emit the SYNTHESIZABLE over-the-wire engine SoC (real Nexys A7 bitstream): the same universal loader/INIT/ interpret/TX logic as emit_wprog_engine_soc_verilog, but with SYNTH_FUNC_F, the WPE_SYNTH_* cap profile, and (* ram_style="registers" *) forced on every config/state memory so the open flow keeps the UART-streamed config in flip-flops. Proven ≡ eval_wprog_config for fitting programs under iverilog, then synthesized through yosys→nextpnr-xilinx to a bitstream.