Function emit_wprog_engine_soc_verilog_hw 

pub fn emit_wprog_engine_soc_verilog_hw(name: &str) -> String

Emit the DEPLOYED hold-safe over-the-wire engine SoC (the real bitstream): same logic as the synth engine, but with the WPE_HW_* cap profile that both synthesizes the loop’s compare correctly under yosys AND stays under the board’s hold-safe FF threshold. Runs loops/branches/writes, recursion (depth ≤3), and small collections over the wire on real silicon; proven ≡ eval_wprog_config (RTL) + loop gate-sim ≡VM.