Function emit_wprog_engine_soc_verilog_backend_rdw 

pub fn emit_wprog_engine_soc_verilog_backend_rdw(
    name: &str,
    caps: [usize; 10],
    backend: MemBackend,
) -> String

Emit the over-the-wire engine with an EXPLICIT backend AND the SIM-ONLY read-during-write collision detectors active (RDW_DETECT=1). The detectors compare each memory’s registered-read address (heap_ra/sf_ra/ file_ra/v_ra) against every same-cycle write address during the interpret phase and $display + count a RDW-COLLISION whenever they coincide — a cross-port read-during-write that a real RAMB36 returns UNDEFINED for but this behavioral sim idealizes as READ_FIRST (old data). This is a DIAGNOSTIC build only; rdw_detect=false (every other entry point) EXCISES the whole detector region so the shipped netlist is BYTE-IDENTICAL to before this feature (the RDW_DETECT parameter is not even injected into the header).