Function emit_wprog_engine_soc_verilog_backend_debug 

pub fn emit_wprog_engine_soc_verilog_backend_debug(
    name: &str,
    caps: [usize; 10],
    backend: MemBackend,
    debug_readback: bool,
) -> String

Emit the over-the-wire engine with an EXPLICIT memory backend AND an on-chip READBACK debug mode. When debug_readback is true the engine, at the load→run boundary (P_CLR done), FIRST streams a DEBUG FRAME back over the SAME UART tx — a fixed diagnostic slice of each major memory — then hands off to the interpret FSM, so real silicon can be compared against the known config-image/heap values byte-for-byte. The DEBUG FRAME is: sync 0xD8, then for each memory in order {cell_kind, cell_op0, cell_op1, blk_term_kind, heap} entries [0..8), each as a 64-bit BIG-ENDIAN word (8 bytes MSB-first, matching the result frame’s byte order), then end byte 0x8D — 1 + 588 + 1 = 322 bytes. The debug FSM walks each address through a REGISTERED BRAM read (issue → wait the latency → capture) and reuses the existing tx byte-sender. debug_readback=false emits RTL BYTE-IDENTICAL to emit_wprog_engine_soc_verilog_backend (the whole debug region is excised + the parameter is not injected). Readback is only meaningful on the ConfigBram streamed engine — asserted here.