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emit_wprog_engine_soc_verilog_backend

logicaffeine_compile::codegen_sva::wprog_engine_rtl

Function emit_wprog_engine_soc_verilog_backend 

Source 
pub fn emit_wprog_engine_soc_verilog_backend(
    name: &str,
    caps: [usize; 10],
    backend: MemBackend,
) -> String
Expand description

Emit the over-the-wire engine with an EXPLICIT memory backend — the first-class “choose the substrate” entry point. Registers/Bram are the proven paths; ConfigBram additionally maps the config image to block RAM (its registered-read FSM is the in-progress large-capacity build). caps[9] (MAXV) sizes the per-block value array v independently of the whole-program MAXCELL total.