Function emit_wprog_engine_soc_verilog 

pub fn emit_wprog_engine_soc_verilog(name: &str) -> String

Emit the UNIVERSAL over-the-wire whole-program engine SoC: one fixed netlist that RECEIVES any fitting program’s flat image + params over a UART, fills its on-chip config memories (the loader FSM), seeds the register file from the params (INIT), runs the interpret st-machine (== eval_wprog_config == the VM), and streams the 64-bit result + run-cycle count back over the UART — then loops for the next program. The engine core (block-record wires, resolve/resolve_arg, the case(st) walk) is the SAME logic proven in emit_wprog_engine_verilog; only the config source (wire vs $readmemh) and the result path (UART vs port) differ. Integer functional units (synthesizable — the sequential div/mod/floordiv/pow datapath lives in the template; func_f is the DSP multiplies only). CLKS_PER_BIT sizes the UART bit period.