pub fn emit_wprog_engine_soc_testbench(
name: &str,
n_vectors: usize,
clks_per_bit: usize,
max_bytes: usize,
) -> StringExpand description
A self-checking testbench that acts as the OVER-THE-WIRE HOST: it $readmemhs the concatenated wire bytes
(wire_<name>.hex), per-vector byte lengths (lens_<name>.hex), and the eval_wprog_config oracle
(oracle_<name>.hex), then for each vector bit-bangs its bytes onto uart_rx, decodes the returned frame
(0xA5 sync + result[63:0] + cycles[31:0] + 0x5A), and checks the result == the oracle. Proves the WHOLE
wire→synthesize→run→wire path ≡ the VM under iverilog.