Constant WPE_STREAM_HEAP 

pub const WPE_STREAM_HEAP: usize = 32768;

Heap depth (words) for the streamed engine. Sized to 2^15 = 32768 — a POWER OF TWO that maps to exactly ONE RAMB36E1 depth-bank at ×1 width (a single RAMB36 is 32768×1), so the whole 15-bit heap_ra addresses one clean tile with NO depth-cascade. This dodges a yosys 0.33 synth_xilinx mis-map: for a heap whose depth is NOT a clean single-tile fit (e.g. the old 20480), memory_libmap picks a wide tile (×9 → 4096 deep) and then FAILS to depth-cascade — it wires every tile to the SAME 12-bit address (heap_ra[11:0]) and drops the top address bits (heap_ra[14:12]), so on silicon (and in post-synth gate-level sim) any heap read/write to an address

= 4096 aliases into the first 4096-word tile and returns garbage. The whole-program transformer’s heap grows past 4096, so it read uninitialized cells and returned the wrong result on the XC7A200T. 32768 >= the model’s working-set (was 20480), fits the BRAM budget, and — being a single-tile power of two — maps with the full 15-bit address on every port. Proven at the netlist level (the synthesized 20480 heap wires heap_ra[11:0] and drops the top bits; the 32768 heap wires the full heap_ra) and by a post-synth gate-level RAMB sim.

DEPTH-BANKING (silicon fix below the netlist). A 32768-deep heap half at ×1 mapped to a RAMB36E1 in ×1-width, 32768-deep mode — whose INTERNAL two-16K-half depth-cascade (address bit 15 tied high on the upper tiles) is the least-fuzzed RAMB corner. prjxray/openXC7 mis-encodes it on the XC7A200T (a small read-only probe reads wrong by ≈1.5·N) even though the gate-level netlist is ≡VM — the defect is BELOW the netlist. The template therefore DEPTH-BANKS the heap into two 16384-deep banks (heap_b0_*/heap_b1_*, selected by heap-address bit 14; in-bank index = bits [13:0]) so each maps to a 14-bit-indexed tile with NO 32K depth-cascade — a better-fuzzed primitive. Behaviorally IDENTICAL to a flat 32768 heap. HEAP stays 32768 (two 16384 banks).