Module wpe_floorplan 

The whole-program engine’s memory, planned against a real process — before place-and-route.

The WPE runs arbitrary LOGOS bytecode streamed over a wire, and it has run on two Artix-7 boards for months. Every number that describes its memory, though, was chosen for an FPGA:

• HEAP = 32768 is a power of two because a RAMB36E1 is 32768x1, so a 15-bit address lands on exactly one tile with no depth-cascade — dodging a yosys memory_libmap mis-map that silently aliased every heap access above 4096 and made the transformer return a wrong answer on silicon. Nothing about any program wanted 32768; the measured working set is ~18,300 words.
• NREG = 512 is a power of two for the same reason, against a measured ceiling of 175. That one is paid for DEPTH times over, because the frame stack sfile is DEPTH x NREG.
• The _lo/_hi split of every 64-bit array exists to force TDP-W36 and dodge a parity-lane mis-wire.

An ASIC has no RAMB tiles, so the first two buy nothing and cost square millimetres. (The third is a stroke of luck: it makes every array exactly 32 bits wide, which is exactly the width of sky130’s SRAM macros, so no width-banking is needed.)

This module therefore SOLVES the profile instead of inheriting it: measured program demands in, a cap profile and a full floorplan out, or a typed refusal. It answers the question that actually gates the tapeout — what does this engine have to give up to fit a shuttle die, and what is left over for the logic — with arithmetic over the real macro inventory in crate::codegen_sva::pdk_target, rather than with a guess that place-and-route discovers eight hours later.

The array table is checked against the emitted Verilog by wpe_floorplan_lock, so an area model that has drifted away from the RTL it describes fails a test instead of a tapeout.

Structs

Placement

WpeArray

One addressed array, exactly as the emitted RTL declares it.

WpeDemands

What the corpus actually demands — every field a MEASURED ceiling across the lowering benchmark suite, never a guess. depth and heap_words are the two that cannot be read off a config and must be obtained by RUNNING the program; they are also the two the hardware gets silently wrong (the engine advances sp past DEPTH with no bound check), which is how a DEPTH=4 engine once shipped against DEPTH=8 programs and answered fib with 8 instead of 21.

WpeFloorplan

A solved floorplan: where every array lives, what it costs, and what is left for the logic.

WpeProfile

The engine’s cap profile — the ten numbers that size every memory in it.

Enums

ArrayRole

What an array is FOR — which is what decides whether it can live off-chip.

Residence

Where one array ends up.

WpeUnplaceable

Why an engine cannot be placed. Typed, so a caller cannot mistake a refusal for a plan.

Constants

ASIC_PROFILE

The ASIC cap profile, DERIVED from MEASURED_SUITE rather than written down.

MEASURED_SUITE

The MEASURED ceiling across the whole lowering benchmark suite, from wprog_all_benchmarks_lane::print_max_dims_across_all_benchmarks (35 programs). depth and heap_words are the two that cannot be read off a config and must be obtained by RUNNING the program — and depth is the one the hardware gets silently wrong, because the engine advances sp past DEPTH with no bound check. That is how a DEPTH=4 engine once shipped against DEPTH=8 programs and answered fib with 8 instead of 21.

Functions

plan_wpe

Plan every array of profile onto pdk, sending the roles in off_chip behind the memory edge, and check the result against the vehicle’s user area alongside logic_cells of engine.