Struct TimingGraph 

pub struct TimingGraph {

    pub nodes: Vec<String>,
    pub edges: Vec<Edge>,
    pub costs: Vec<Cost>,
    pub owner: Vec<usize>,
    pub instances: Vec<String>,
    pub flops: usize,
    pub area: Vec<Area>,
    pub public: Vec<bool>,
    pub inputs: Vec<usize>,
    pub outputs: Vec<usize>,
    pub structure: Option<Structure>,
    pub boxes: Vec<Boxed>,
    pub fanout: Option<Fanout>,
}

A timing graph: a node per net bit and per internal point of a carry chain, DSP block or memory.

Fields

nodes: Vec<String>

Each node’s name: the net’s name and bit, or the cell’s and its point.

edges: Vec<Edge>

costs: Vec<Cost>

What each edge adds, by kind, for a graph read from a netlist (TimingGraph::reweigh); empty for one built by hand.

owner: Vec<usize>

The instance whose cell made each edge, an index into instances.

instances: Vec<String>

Instance paths in the form Quartus prints them, |-separated; the top is "".

flops: usize

Flip-flop bits.

area: Vec<Area>

What each instance’s own cells take, by instance (TimingGraph::area_under sums a subtree).

public: Vec<bool>

Whether each node is a bit of a net the design names (a signal of its source, not one synthesis made).

inputs: Vec<usize>

The module’s input and output port bits, ports by name and each one’s bits in order.

outputs: Vec<usize>

structure: Option<Structure>

How each node is made, when the graph was read from a netlist: what writing it back out as Verilog needs.

boxes: Vec<Boxed>

The instances of modules timed apart.

fanout: Option<Fanout>

The loads each net drives and what drives it, for a graph read from a netlist; none for one built by hand.

Implementations

impl TimingGraph

pub fn area_under(&self, path: &str) -> Area

What instance path and every instance under it take (Area); the top is "", the whole graph.

pub fn arrivals(&self) -> Result<Vec<i64>, TimingError>

Each node’s arrival: the deepest combinational path ending there.

pub fn fanouts(&self) -> Vec<u64>

How deep the logic is, overall and through every instance. Each node’s loads: the cell inputs it reaches, a memory port counted as the blocks it reaches; every edge one load in a graph built by hand.

pub fn wide(&self, logic: u64, register: u64) -> Vec<Wide>

The nets past their bound, widest first (ties by name): those logic or a memory drives past logic loads, a register past register — a register whose net asks for at most N loads (maxfan) being copies of N each, past it only when N is — an input past logic (whatever drives it outside); a box’s outputs are the box’s to bound, a clock rides a clock network, and a point inside a cell is no net. Empty for a graph built by hand.

pub fn depth(&self) -> Result<Depth, TimingError>

pub fn reweigh(&mut self, delays: &Delays)

Every edge’s delay from its cost at delays: the graph as reading its netlist at delays makes it.

pub fn cost(&self, edges: &[usize]) -> Cost

What edges add together.

pub fn endpoints(&self) -> Result<Vec<Endpoint>, TimingError>

The deepest path into each register and each output, deepest first. A register’s path ends at its input: a delay on a registered edge counts after the register, in the next stage.

pub fn loop_bound(&self) -> Result<Bound, GraphError>

The bound the design’s loops put on its clock, in the graph’s delay unit per register.

pub fn name_loop(&self, bound: &Bound) -> Vec<String>

A bound’s loop, node by node in order, a register’s output marked with the registers it comes out of.

Trait Implementations

impl Clone for TimingGraph

fn clone(&self) -> TimingGraph

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for TimingGraph

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for TimingGraph

fn default() -> TimingGraph

Returns the “default value” for a type.