Function fill_verilog 

pub fn fill_verilog(template: &str) -> String

Fill a terminal Verilog template from this module: __V_<NAME>__ becomes a byte as a Verilog literal (8'hC0), __X_<NAME>__ the hex a comment quotes (0xC0), __N_<NAME>__ a decimal number, __C_<NAME>__ a colour (12'hFFF), __PALETTE_CASE__ the palette as case arms (4'd1: palette = 12'h00A;), __HEAT_CASE__ the heat ramp the same way, and __DIGIT_ROM_CASE__ the font’s digit glyphs keyed {digit, row}. Panics on a placeholder this module does not define, so a template cannot name a value nobody owns.