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eval_systolic_pipelined_acc

logicaffeine_compile::codegen_sva::systolic

Function eval_systolic_pipelined_acc 

Source 
pub fn eval_systolic_pipelined_acc(
    sys: &Systolic,
    acts: &[i64],
    m: usize,
    bits: u32,
    acc_bits: u32,
) -> (Vec<i64>, usize)
Expand description

eval_systolic_pipelined with an explicit accumulator width acc_bits — the partial-sum register wraps (two’s-complement) at acc_bits, exactly like the acc_bits-wide ps_reg in the emitted RTL. With acc_bits = 64 this is bit-identical to eval_systolic_pipelined; with ACC_BITS_MXU it models the int32-accumulator tape and is lossless whenever the true accumulation fits (guarded in the lock).