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eval_systolic_pipelined

logicaffeine_compile::codegen_sva::systolic

Function eval_systolic_pipelined 

Source 
pub fn eval_systolic_pipelined(
    sys: &Systolic,
    acts: &[i64],
    m: usize,
    bits: u32,
) -> (Vec<i64>, usize)
Expand description

Cycle-accurate golden model of the pipelined weight-stationary array — steps the register planes exactly as the emitted RTL does (activation EAST, partial-sum SOUTH, on-chip skew/de-skew), so the RTL must match it cycle-for-cycle. Returns (O row-major, L) where O ≡ eval_systolic_bits (the math is unchanged; only the timing differs). acts is m*k row-major.