Function eval_systolic_os_pipelined 

pub fn eval_systolic_os_pipelined(
    os: &SystolicOs,
    a: &[i64],
    w: &[i64],
    bits: u32,
) -> (Vec<i64>, usize)

Cycle-accurate output-stationary model — mirrors the RTL register-for-register. Activation A[i][t] enters row i skewed by i, flows east; weight W[t][j] enters col j skewed by j, flows south; every cycle each PE does acc <= acc + a_in·w_in (skew/drain fill zeros contribute nothing). At PE(i,j) on cycle T both operands carry contraction index t = T-i-j, so acc[i][j] converges to O[i][j]. Returns (O, latency) with latency = pipelined_os_latency.