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emit_systolic_verilog_bits

logicaffeine_compile::codegen_sva::systolic

Function emit_systolic_verilog_bits 

Source 
pub fn emit_systolic_verilog_bits(
    name: &str,
    sys: &Systolic,
    bits: u32,
) -> String
Expand description

Emit the weight-stationary array at a chosen integer precision bits (8/16/32/64) — the precision dial’s RTL (Phase 4). Operands are the low bits of each input, sign-extended; weights baked as sign-extended two’s-complement constants. Matches eval_systolic_bits for ALL inputs.