Function emit_systolic_verilog 

pub fn emit_systolic_verilog(name: &str, sys: &Systolic) -> String

Emit the registered weight-stationary array as synthesizable Verilog. Ports: clk, rst, the k activation inputs a0..a{k-1} (64-bit; the low 8 bits are the int8 operand), and the n registered outputs o0..o{n-1}. Weights are baked as signed 64-bit constants (the sign-extended int8). One output row is produced per clock; o{c} on cycle t+1 is the dot of the activation row applied at cycle t.