Function emit_systolic_pipelined_verilog_bits_acc 

pub fn emit_systolic_pipelined_verilog_bits_acc(
    name: &str,
    sys: &Systolic,
    bits: u32,
    acc_bits: u32,
) -> String

Emit the pipelined, register-staged weight-stationary systolic array at operand precision bits and accumulator width acc_bits. Structure (matches eval_systolic_pipelined_acc register-for-register): per PE an activation register (a_reg, flows EAST, bits wide) and a partial-sum register (ps_reg, flows SOUTH, acc_bits wide) with ps_reg[r][c] <= ps_in + a_in·W[r][c] — the only combinational path between flip-flops is one bits×bits multiply + one add, so the critical path does NOT grow with K. On-chip input-skew (row r delayed r cycles) and output de-skew (col c delayed N-1-c) keep the clean clk/rst/a0..a{k-1}/o0..o{n-1} interface; o{c} on cycle t holds output row t-L (L=K+N-1). Narrowing acc_bits to ACC_BITS_MXU shrinks the inter-PE bus for a congestion-free tape and is lossless while the true accumulation fits acc_bits (guarded in the lock).