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emit_systolic_pipelined_verilog_bits

Function emit_systolic_pipelined_verilog_bits 

Source
pub fn emit_systolic_pipelined_verilog_bits(
    name: &str,
    sys: &Systolic,
    bits: u32,
) -> String
Expand description

Emit the pipelined weight-stationary array at precision bits with a full (64-bit) accumulator.