Function emit_systolic_pipelined_verilog 

pub fn emit_systolic_pipelined_verilog(name: &str, sys: &Systolic) -> String

Emit the PIPELINED weight-stationary array (int8) as synthesizable Verilog. See emit_systolic_pipelined_verilog_bits; the critical path is ONE mul + ONE add (K-independent).