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emit_systolic_pipelined_loadable_verilog

logicaffeine_compile::codegen_sva::systolic

Function emit_systolic_pipelined_loadable_verilog 

Source 
pub fn emit_systolic_pipelined_loadable_verilog(
    name: &str,
    k: usize,
    n: usize,
    bits: u32,
    acc_bits: u32,
) -> String
Expand description

A weight-stationary PE array whose weights are loaded through a port and hold what they power up with until then: pe_array_verilog(.., Loaded(PowerUp)). Cycle-for-cycle identical to the baked array once the same weights are loaded (locked).