Function emit_systolic_os_streaming_verilog 

pub fn emit_systolic_os_streaming_verilog(
    name: &str,
    os: &SystolicOs,
    bits: u32,
    acc_bits: u32,
) -> String

Emit the output-stationary array for tile after tile. Ports: clk/rst, first (high on each tile’s first contraction beat), aw{i} / wn{j} (the un-skewed operand streams of emit_systolic_os_pipelined_verilog_bits_acc) and res{i}_{j} (the finished sums of the previous tile). first rides the activation wavefront, so it reaches PE(i,j) with the tile’s first products: there the PE moves its sum into res_reg and restarts from that product — no reset and no idle beat between tiles. Column j’s result waits os_streaming_deskew cycles, so each row is readable all at once at os_streaming_result_offset.