Function emit_systolic_os_pipelined_verilog_bits_acc 

pub fn emit_systolic_os_pipelined_verilog_bits_acc(
    name: &str,
    os: &SystolicOs,
    bits: u32,
    acc_bits: u32,
) -> String

Emit the register-staged output-stationary array at precision bits. Ports: clk/rst, aw{i} (west activation stream for row i), wn{j} (north weight stream for col j), and acc{i}_{j} (the stationary accumulator outputs, continuously readable). Per PE: a_reg (flows east), w_reg (flows south), acc_reg <= acc_reg + a_in·w_in. The only combinational path between flip-flops is one mul + one add — K-independent, exactly like the weight-stationary pipelined tile. Skew of the streamed operands is applied on-chip (row i / col j delayed i / j cycles), so the caller drives un-skewed streams.