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emit_simt_ports_verilog

logicaffeine_compile::codegen_sva::simt_ports

Function emit_simt_ports_verilog 

Source 
pub fn emit_simt_ports_verilog(
    name: &str,
    eng: &SimtEngine,
    cut: impl Fn(usize) -> bool,
) -> Result<SimtPorts, String>
Expand description

Emit eng’s step on ports as module name: inputs clk, a, b, mask (when the engine is predicated) and x0.., outputs y0.. and reduced (when it reduces). Refused unless the lane kernel computes a·x + b with a and b uniform and x per lane, and its reduce, if any, is an Add, Or, Xor or And: those fold a tree of lanes to the same word as the engine’s fold from the op’s identity.