Function emit_simd_fadd_f32x2_verilog 

pub fn emit_simd_fadd_f32x2_verilog() -> String

Emit the packed F32×2 add tile: two fp32_add lanes (low = bits [31:0], high = [63:32]) driven in parallel from the 64-bit operands. Module name simd_fadd_f32x2 (ports a,b,r), so the standard SIMD testbench drives it. Compile alongside FP32_ADD_V; proven ≡ eval_lanewise_fadd_f32x2 under iverilog.