Function emit_simd_add_verilog 

pub fn emit_simd_add_verilog(name: &str, ty: LaneTy) -> String

Emit the packed SWAR add as a COMBINATIONAL Verilog module — the SIMD tile the RTL flow tapes out: r = ((a & M) + (b & M)) ^ ((a ^ b) & ~M), one datapath op, carry blocked at every lane boundary. Proven ≡ the lane-wise spec under iverilog by simd_rtl_lock (and ≡ N scalar adds by SAT in simd_tile_lock).