Module sequencer_rtl 

sequencer_rtl — Stage 1 of the self-synthesizing bytecode XPU: the AUTONOMOUS block-walk sequencer as synthesizable RTL. The CONTROL PLANE that run_program_cfg_on_grid modelled in software now exists in silicon: a register file that survives block reconfiguration, per-block placed grids, a block program- counter, a terminator FSM (Jump/Branch/Return), and a cycle counter — a hardwired micro-sequencer that walks the whole function itself, one block per clock, with no host help.

It is the RTL of exactly run_program_cfg_on_grid’s loop (fabric_grid.rs): each basic block’s straight-line body is PLACED on a fresh tile array by route_loop_body (the block’s live-in registers as inputs; its register writes then its terminator operand as the grid’s outputs, in that order — the all_outs() order the placer guarantees). Every block’s grid is a combinational island wired to the CURRENT register file; on each clock the sequencer latches the ACTIVE block’s writes back into the file and follows its terminator: a Jump sets the next block, a Branch lets the block’s predicate output pick the successor, a Return captures the operand and halts. So the whole branchy program runs as spatial dataflow driven by a tiny sequencer — proven bit-identical to run_program_cfg_on_grid (≡ eval_program_cfg_fabric ≡ the VM) under iverilog by fabric_sequencer_lock.

The block grids are emitted by the existing emit_grid_verilog (multi-output form); this module adds only the register file + sequencing FSM around them. Blocks are Arith/Select/Func islands (the stateless control plane); the heap state plane is the Stage-2 follow-on (sequencer_rtl gains a shared BRAM there).

Functions

emit_sequencer_testbench

A self-checking testbench for the sequencer: for each vector, load the params, pulse reset, run the FSM to done, and compare BOTH result and cycles to the VM oracle in seq_{name}_{out,cyc}.hex (inputs in seq_{name}_in.hex). The step-count check pins the trajectory, not just the answer.

emit_sequencer_verilog

Emit the autonomous block-walk sequencer for a whole-function CFG fabric: the per-block placed-grid modules followed by a seq_{name} top that carries the register file + block-PC + terminator FSM + cycle counter. One block step per clock; done pulses high with the return value on result and the block-step count on cycles.

eval_sequencer

Evaluate a whole-function CFG fabric on the sequencer’s model and return (result, block_steps). This IS run_program_cfg_on_grid — the same place-per-block (route_loop_body) + eval_grid_all walk over a register file — with a step counter added, so the returned value is identical to the grid walk (≡ the CFG model ≡ the VM) and block_steps is the exact number of block executions the RTL must take (the trajectory, not merely the answer). The reference the iverilog differential checks against.