Function emit_secded_verilog 

pub fn emit_secded_verilog() -> String

Emit the SECDED(72,64) encoder + decoder/corrector as synthesizable Verilog, generated from the SAME incidence as encode/decode, so they cannot diverge. Interface: enc takes 64-bit din → 72-bit cw; dec takes a 72-bit cw_in → 64-bit dout + corrected + double_err.