Function emit_reconfig_fabric_verilog 

pub fn emit_reconfig_fabric_verilog(
    name: &str,
    rows: usize,
    cols: usize,
    n_in: usize,
) -> String

Emit the universal reconfigurable fabric: a fixed rows×cols config-driven CGRA. Each tile decodes its control word (loaded via $readmemh) into an operation + channel routing and computes the same feed-forward dataflow the hardwired grid does; loading route_loop_body’s certified placement runs any bounded Arith block on this ONE array. Combinational (feed-forward south/east) — the answer settles in zero clocks; the config is read once at elaboration.