Module reconfig_fabric_rtl 

reconfig_fabric_rtl — Stage 4 of the self-synthesizing bytecode XPU: the placer IN SILICON as a RECONFIGURABLE fabric. Stage 1 HARDWIRED a grid per block; Stage 3 proved route_loop_body correct for every bounded body. This stage makes the fabric CONFIG-DRIVEN: ONE fixed R×C tile array whose every tile’s operation and channel routing are RUNTIME inputs, so loading the certified placement of ANY block runs it on the same physical silicon — the reconfigurable array the on-chip placer configures.

A tile’s config is a 32-bit control word (alu op + the two operand sources + the vs/he channel drives) plus two 64-bit constant slots (for Const operands). serialize_grid_config transcribes a placed Grid (from route_loop_body, padded to the array size) into that config; the emitted fabric decodes it per tile and computes the same feed-forward dataflow the hardwired grid does. Proven ≡ the VM under iverilog by reconfig_fabric_lock: for a corpus of straight-line programs, the certified placement loaded into ONE universal array computes exactly what the VM computes.

Correct-first scope: Arith-tile grids (the Stage-3 certified family) with a single Val output — the spatial place-and-route the array runs is route_loop_body’s canonical placement. Select/Func/Mem tiles and the on-chip placement of the config (the placement decode moving from host to chip) are the follow-ons; here the certified placement is loaded, and the ARRAY is proven universal + reconfigurable.

Structs

ReconfigConfig

A placed grid transcribed into the reconfigurable fabric’s config: one 32-bit control word per tile, two 64-bit constant slots per tile (operand a/b Const values), and the output tap (out_sel = flat tile index, out_chan = 0 for the vertical channel / 1 for the horizontal).

Functions

emit_reconfig_fabric_verilog

Emit the universal reconfigurable fabric: a fixed rows×cols config-driven CGRA. Each tile decodes its control word (loaded via $readmemh) into an operation + channel routing and computes the same feed-forward dataflow the hardwired grid does; loading route_loop_body’s certified placement runs any bounded Arith block on this ONE array. Combinational (feed-forward south/east) — the answer settles in zero clocks; the config is read once at elaboration.

emit_reconfig_testbench

A self-checking testbench for the reconfigurable fabric: drive each input vector and compare result to the VM oracle in reconfig_{name}_{pin,eout}.hex (the fabric loads its config from reconfig_{name}_{ctrl,sac,sbc,out}.hex). One block’s config + vectors are written per run; the fabric RTL is fixed, so it compiles once and re-runs per block.

serialize_grid_config

Transcribe a placed Grid (Arith tiles, single Val output) into the reconfigurable fabric’s config, laid out row-major over rows*cols tiles (the grid must already be padded to rows×cols).