Function emit_pass_wrapper 

pub fn emit_pass_wrapper(
    name: &str,
    top: &str,
    clock: &str,
    reset: Option<&Reset>,
    ports: &[DutPort],
) -> String

The power block <name> of a design measured without a functional harness — a memory controller, driven at gate level by the K7 traffic testbench: its clock and reset renamed clk and rst (active high), every other port passed straight through under its own name, the design kept whole as u_dut, so the flow’s cells are told apart from its own. A port named clk or rst that is not the clock or reset would collide, and is refused.