pub fn emit_fold_wrapper(
name: &str,
top: &str,
clock: &str,
reset: Option<&Reset>,
ports: &[DutPort],
) -> StringExpand description
The synthesis wrapper qorsyn_<name>(clk, rst, sig) of a design measured without a functional
contract (a memory controller, whose functional gate is a board memtest): every input of top
from a register the seeded xorshift64 stimulus refills each cycle, one rotated lane word per 64
bits as the harness draws operands; every output bit folded into a registered 64-bit XOR whose low
16 bits are sig; the design kept whole as u_dut, so its cells and its register-to-register
paths are what synthesis and place-and-route measure.