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emit_psram_model_verilog

Function emit_psram_model_verilog 

Source
pub fn emit_psram_model_verilog(p: &PsramPart) -> String
Expand description

A pin-level model of the part: its semantics (SPI until Enter-QPI, Reset-Enable + Reset before use, bursts wrapping inside a page) and every rule it checks — the timing rules, an SIO bit the part samples that nobody drives (float), and a host driving against the part’s read data (contend) — each counted by name on a PSRAM-VIOLATION <rule> line. violations holds the total.