pub fn emit_psram_edge_verilog(edge: &PsramEdge) -> StringExpand description
The controller. One request is one burst: req_len words at word address req_addr. A write
takes wdata at the start of each word (pulsing wdata_take); a read returns each word on
rdata with a one-cycle rdata_valid. req_ready is high whenever a request can be taken.