Function emit_psram_cache_verilog 

pub fn emit_psram_cache_verilog(cache: &PsramCache) -> String

The cache. Its engine side is a registered-read memory port: ra holds the read address and rd is data[ra] one cycle later, refreshed every cycle, so a resident line reads exactly as a block RAM does; req_r/req_w pulse the cycle after the engine issues a read or a write, whose address, data and half-word enables wm hold until its next one. busy is high while a miss is served — a dirty victim written back, then the line filled, with a write miss merging its enabled halves into the fill — and while a read issued together with a write waits for it.

busy freezes the whole engine, so it takes no tag lookup of ra or wa: rhit/whit are their hits, which the engine registers beside each address as it sets it, looking the new address up in the lines as they will hold after that edge (emit_psram_cache_hit_function) — the same value, a cycle earlier, so the engine stalls in exactly the cycles it did. The cache exports what that lookup reads (tags, vals, and the line a fill installs at this edge: filled, fidx, ftag); in simulation it counts every cycle a registered hit disagrees with its lines (hit_mismatches, a PSRAM-CACHE-HIT-MISMATCH line each).