pub fn emit_psram_cache_testbench(
edge: &PsramEdge,
cache: &PsramCache,
run_period_ps: u32,
seed: u32,
words: u32,
ops: u32,
) -> StringExpand description
A randomized testbench for the cache: an engine-shaped driver that issues nothing while busy and
otherwise a read (then waits a cycle and checks rd against a reference memory), a write of one or
both halves of a word, or a write and a read together. Once the edge has initialized the part it writes every word it will use — words
consecutive from 0 and words scattered over the whole part — then runs ops random operations.
Prints CACHE-ERRORS, PSRAM-VIOLATIONS, the longest busy run as CACHE-MAX-STALL, the rising edge
after reset at which req_ready was first seen as EDGE-READY-AT, then CACHE-DONE. The clock runs at
run_period_ps, anywhere in the edge’s range.