Function emit_psram_arbiter_verilog 

pub fn emit_psram_arbiter_verilog() -> String

Several caches share one edge. When the edge is idle the lowest-numbered requester is granted and its request goes to the edge; that cache owns the edge until the burst completes and sees c_ready exactly once more when it does, in a cycle in which no other cache is granted. The edge’s write-data takes and read strobes go to every cache: only the owner is ever in a burst state, the only states that listen.