Module plasticine_place 

Mesh placement + static routing for a Plasticine configuration — P3 of the Plasticine lane.

Given a Metapipeline (stages with their datapath depth and cell count) and the words each inter-stage buffer must hold, this allocates PCUs and PMUs, places them on the checkerboard, routes every edge with dimension-order (X then Y) static routing, and reports what an RDU engineer asks for: PCU/PMU used vs total, FU utilization, hop counts, per-link occupancy against the switch’s link budget, and whether the static routing fit. Every stage’s datapath is still the SAT-certified placement of FabricTarget::plasticine_shaped (P0) — this module only decides WHERE on the mesh and HOW MANY.

Model (ISCA’17 §3.1–3.3, §3.6 “hierarchical binding”; Spade defaults for link counts): a scalar body of critical depth D and C cells chains ceil(max(D, C) / pcu_stages) PCUs (a lane owns one FU per stage: depth needs stages, cells need slots), each PCU running pcu_lanes iterations in parallel; a buffer written in stage i and read in stage j is j-i+1-deep N-buffered inside one PMU when it fits words_per_pmu / depth, else spans ceil(words / (words_per_pmu / depth)) PMUs; the checkerboard alternates PCU/PMU cells; routes follow X-Y order and each DIRECTED mesh link carries at most vector_links vector routes; a stage that takes no PCU (a perimeter address generator) enters the mesh at the edge switch of its neighbour’s row, one extra hop. MODELED; never a Plasticine simulation.

Structs

Allocation

BufferAllocation

PMUs one buffer edge needs.

LinkBudget

Switch/link budget per mesh segment (Spade SpadeConfig defaults: vlink 2, slink 4, vc 4).

MeshNet

One vector net to route.

MeshRouting

The vector nets of one placement, routed. For every net, in order: the mesh links it occupies, and its occupancy keys — (link, 0) for a channel of a directed link, ((cell, cell), 1) for a perimeter port carrying DRAM → mesh and ((cell, cell), 2) for mesh → DRAM — so that the largest count over keys of a legal routing never exceeds the channel budget.

Placed

Placement

Route

A routed edge: PCU (writer chain tail) → PMU → PCU (reader chain head), with its hop count.

StageAllocation

PCUs one stage needs.

Enums

Endpoint

A net endpoint on the mesh.

Unit

A placed unit on the checkerboard.

Traits

MeshRouter

A router for the mesh’s vector nets. place_unrolled places with row-balanced cells and routes through the installed router (place_routed), or falls back to place’s xy-static routes when none is.

Functions

allocate

Allocate PCUs/PMUs for mp on t; buffer_words[i] is the tile size flowing over mp.edges[i]. Every stage is hosted on PCUs.

allocate_hosted

allocate with the stages listed in ag_stages hosted on the PERIMETER ADDRESS GENERATORS (ISCA’17 §3.4: the AGs at the chip’s edges drive the DRAM tile loads and stores) rather than on PCUs: such a stage takes no PCU and places no FU stage; place routes it from the mesh edge.

dram_streams

Perimeter DRAM ports one instance of mp needs, (into the mesh, out of the mesh): every buffer edge written by a perimeter-hosted stage is one inbound stream, every edge read by one is one outbound stream (each PMU of a spanning buffer is its own stream).

install_mesh_router

Install this process’s mesh router, once; Err hands back the argument when one is already installed. Certified place-and-route installs its congestion-negotiating router this way, from its own side: the compiler never depends on it, so the published tree builds without it.

lanes_need_banks

The capability a placement demands of the descriptor beyond depth: at least one bank per lane for a conflict-free vector access (Plasticine: 16 banks for 16 lanes).

max_par

The widest unroll factor whose replicated allocation fits t by CAPACITY (at least 1 when one instance fits) — PCUs, PMUs, and the perimeter DRAM ports (rows × 2 sides × vector_links per direction, ISCA’17 §3.4–3.5) — before routing is considered.

max_routable_par

The widest unroll that fits t AND routes statically within budget — the routability-aware unroll (the static vector network’s perimeter ports, not PCU/PMU capacity, bound a DRAM-fed unroll first on a large mesh). Returns (routable, capacity); routable == 1 is reported even when a single instance exceeds the budget, so a row can still say routed_statically: false honestly.

max_routable_par_within

max_routable_par searching below upper (capped at capacity) — for an unroll that the work itself bounds below capacity (fewer outer iterations than instances). The search is a BISECTION over [1, upper]: routability is treated as monotone in the unroll (more instances, more perimeter streams), so the result is the widest unroll the bisection finds routable — a stalled negotiation at some intermediate width would hide a wider routable one, which is the honest limit of a heuristic router without the exact rung on the full problem.

mesh_router

The installed mesh router, if any.

place

Place the allocation on the checkerboard in pipeline order (a row-major snake over PCU cells, each stage’s chain contiguous, each edge’s PMU(s) taken from the PMU cells nearest the writer’s tail), then route every edge X-Y and count link occupancy against the budget.

place_metapipeline

Allocate + place in one call.

place_routed

Place alloc on the checkerboard with row-balanced PCU cells and each edge’s PMU(s) on the free PMU cells nearest its writer and reader (a perimeter-hosted end pulls the PMU toward the nearer side), then route every vector net — writer tail → PMU → reader head per buffer, DRAM ↔ PMU for perimeter-hosted stages, and the PCU→PCU links inside every chain (reported as a route on the self-edge (stage, stage)) — through router, whose independent legality verdict is routed_statically. max_link_occupancy counts the channels one directed link — or one direction of a perimeter port — carries (never above the budget when legal).

place_unrolled

Allocate mp (with ag_stages on the perimeter address generators) once, unroll it par ways, and place every instance — a typed TooSmall when the replicated allocation exceeds the mesh.

pmus_for

PMUs a depth-deep N-buffer of words needs on t: a PMU’s address space is partitioned depth ways (Spatial’s N-buffering), so one PMU holds words_per_pmu / depth words per buffer; an empty tile still occupies one PMU (the buffer exists).

words_per_pmu

32-bit words one PMU holds (ISCA’17: 16 banks × 16 KB = 256 KB = 65,536 words).

Type Aliases

Link

A mesh link ((r,c),(r',c')); a link whose ends coincide is a perimeter port of that edge cell.