pub fn script_cut(
top: &str,
params: &[(&str, &str)],
undefined: Undefined,
units: &[&str],
) -> StringExpand description
script_reading with every instance of the units modules cut out: each module read from units.v as its ports
alone (read_verilog -lib, its body never elaborated; a module no unit is named is an error), and once the design
is flat and written, each instance turned
into ports of the top (expose -evert) — its outputs inputs named <instance>.<port>[bit], its inputs outputs of
the same names.