pub fn module_graph(
verilog: &str,
module: &str,
through: &[&str],
) -> Result<Graph, NetlistError>Expand description
The instances of module in verilog as a floorplan’s wires: each pair of its instances and the bits between them,
and each instance and the bits between it and the module’s own ports. The modules through names are dissolved into
it (flatten), so their instances are the module’s, named by path (fast|unit; a generate block’s
lane_port[0].port); every other module is read by its ports alone (read_verilog -lib), so nothing under an instance
is elaborated. The bits between two ends are the nets one drives and the other reads, and what each drives into the
other through the module’s own logic (its registers, multiplexers and the rest, one cell or more): the fewer of the
nets leaving the one and the nets arriving at the other, so a bus through a register stage counts its width and a
select steering a bus one bit. A net two ends only read joins neither to the other: a broadcast is a star from its
driver, not a wire between every two of its readers. A glue cell’s clock pins carry no bits: the clock network is no
wire a floorplan shortens.