Function clock_sources 

pub fn clock_sources(
    verilog: &str,
    top: &str,
    params: &[(&str, &str)],
) -> Result<Vec<ClockSource>, NetlistError>

Every net that clocks a register or a memory port of top with its parameters set, flattened: what drives it and the register bits it clocks, the nets no port drives first, then by the bits they clock. A clock a register or logic makes inside a design reaches no global network unless the fitter gives it one, and a persona’s region cannot; it rides general routing, its skew paid for in the delay the router adds for hold, so a design is refused such a clock before it is fitted.