Module memsched 

memsched — the static-memory-schedule FACT.

The chip’s keystone claim is “the memory access schedule is fully static.” This module turns that from prose into a measurement: every ISA op is classified by its memory behavior (EXHAUSTIVE match — a new op cannot compile unclassified, the same pit-of-success shape as vm::isa::silicon_status), index registers are classified by a flow-insensitive fixpoint (Const / Induction / Opaque), and a program gets a per-site verdict: what fraction of its datapath memory sites have a compile-time schedulable address stream.

The analysis deliberately UNDER-approximates (flow-insensitive; anything unproven is Opaque → dynamic), so the reported fraction is a FLOOR — exactly what the ratchet in logicaffeine_tests/tests/memsched_lock.rs wants: floors only rise.

Vocabulary (what the DRAM scheduler in codegen_sva::dram consumes): • static site — address stream known at compile time: allocation, sequential append/scan/copy (a DMA descriptor), constant-offset field/global slot, or an element access whose index register is a constant or a linear induction variable; • dynamic site — data-dependent address: gather/scatter via an unproven index, or a hash-structure access (set/map); • coprocessor site — I/O, time, channels, tasks, network, kernel builtins: off the memory datapath entirely (they live on the NoC / service units, not the DRAM edge).

Structs

CachePlan

The software-managed-cache plan for a program (GAPS G19, MEMORY_EDGE_SPEC.md §3): the datapath memory sites partitioned into prefetch (compile-time-known address stream — served from the static schedule, zero runtime miss, zero-jitter) and probe (data-dependent — a tag probe that may miss and fall back to the managed cache). pc values index CompiledProgram::code.

MemSchedReport

The measured verdict for one program.

Enums

RegClass

The address class of a register within one code segment (one function body).

SiteKind

The memory shape of one ISA op. Exhaustive over every variant — no wildcard.

Functions

analyze

Analyze a compiled program: classify every op site, resolving indexed sites against the enclosing function segment’s register classes.

cache_plan

Build the managed-cache plan: exactly the memsched static/dynamic partition, so the probe list — the ONLY sites that can miss — equals the compiler’s dynamic_sites, and streaming kernels (all-static) produce an EMPTY probe list (they never touch the managed-cache path, preserving their zero-jitter contract).

explain_dynamic_sites

Human-readable diagnosis of the first limit DYNAMIC sites: which op, which index register, and every write shape that register has in its segment — the tool for understanding why a kernel’s fraction is what it is (and for sharpening the floor).

site_kind

Classify one op’s memory behavior. EXHAUSTIVE — adding a VM op forces a decision here.