Function emit_keccak_core_half_verilog 

pub fn emit_keccak_core_half_verilog() -> String

Emit keccak_core_half: the iterative core with a register between theta and the rest of each round, two clocks a round (48 for the permutation), each half carrying only its own wiring — theta’s column parities, then rho and pi’s lane moves into chi. The same ports and handshake as keccak_core.