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emit_gpu_simt_testbench

logicaffeine_compile::codegen_sva::gpu_simt_rtl

Function emit_gpu_simt_testbench 

Source 
pub fn emit_gpu_simt_testbench(
    name: &str,
    eng: &SimtEngine,
    n_vectors: usize,
) -> String
Expand description

A self-checking iverilog testbench: for each of n_vectors vectors, reset the load counter, stream the load slots from gpu_{name}_in.hex, pulse go (all lanes compute in one cycle), then read back every lane output + the reduced scalar via raddr and compare against the VM oracle in gpu_{name}_out.hex. Prints PASS/FAIL. Layout matches write_gpu_hex.