Module full_asm 

full_asm — assemble a compiled LOGOS program (register bytecode CompiledProgram) into the instruction words the FULL soft-core (soft_core.v) executes: the whole 113-op ISA — user functions (hardware arg-copy Call), division/modulo (the sequential shared divider), and the structured heap (lists, tuples, ranges, sets, maps, structs) — so the ENTIRE benchmark suite compiles from .lg source to words that run on silicon byte-identically to the VM.

Unlike scalar_asm (the function-free combinational subset), this targets the full datapath and lays out Main + every function body in one imem image. The op BYTE is always binisa::opcode(op) — the append-only ISA ABI the hardware decoder keys on — and every operand field is packed exactly as codegen_sva::rtl::run_soft_core decodes it (the ≡VM software model is the field-layout spec).

Locked ≡ VM by rtl.rs::tests::encode_full_matches_vm.

Functions

compile_to_full_words

Compile a .lg source all the way to full soft-core imem words, through the chip compile path (compile_for_chip — plain Div/Mod, no magic reciprocals). Err if it doesn’t parse/compile or uses anything outside the chip’s integer subset. Targets the 32-bit datapath (the tape-out core); for a 64-bit datapath (VM parity on 64-bit-range arithmetic) use compile_to_full_words_w.

compile_to_full_words_w

The WIDTH-PARAMETRIC form of compile_to_full_words: compile .lg source to full soft-core imem words for a datapath of width bits (32 = the tape-out core, byte-identical to the historical output; 64 = full-i64 VM parity — a constant that exceeds i32, like the benchmark PRNGs’ % 2147483648 / % 4294967296 moduli, is emitted as a 3-word LoadConstWide64 instead of being truncated). Pair with crate::codegen_sva::soft_core_model::run_soft_core_w at the SAME width.

encode_soft_core_full

Assemble a whole compiled program (from crate::vm::Compiler::compile_for_chip) into full soft-core imem words. TWO-PASS: pass 1 lays out Main then every function body, computing each code index’s imem word offset (a Call and a wide LoadConst occupy two words); pass 2 emits the words, resolving every Jump/branch/iter target and callee entry through that pc→imem map. Err if the program uses an op with no chip lowering (floats, Text, closures, CRDTs, channels, …) or overflows an operand field.

encode_soft_core_full_w

The width-parametric form of encode_soft_core_full. width is retained as an API/experimental knob describing the runtime datapath’s fast-path size, but it NO LONGER changes the emitted image: every over-i32 constant is a 3-word LoadConstWide64 (op 222) carrying the full i64 at every width, and the value plane auto-promotes to BigInt on overflow exactly like the VM’s unbounded Int. So the full core reproduces the VM EXACTLY — every constant and every arithmetic result, into the BigInt tail — and does so identically at width 32 and 64 (BigInt handles exactness; the width is a perf/area knob, not a correctness switch). Runs on crate::codegen_sva::soft_core_model::run_soft_core_w at the matching width. (The distinct 32-bit tape-out core in scalar_asm.rs genuinely wraps at 2³² — that is the small-area chip.)

to_hex

Render imem words as a .hex file body (one 8-hex-digit word per line).